The present invention relates to a semiconductor integrated circuit device and a process for manufacturing the same and, more particularly, to a technique effective when applied to a structure for relieving a fault of a DRAM (Dynamic Random Access Memory).
A DRAM, which is provided with a memory array including a plurality of word lines and a plurality of bit lines so arranged as to intersect each other at a right angle, and a plurality of memory cells arranged at the individual intersections, is equipped with a preparatory redundancy circuit including cells in a portion of the memory array and having the same structure and size as those of normal memory cells, so that a faulty product percentage may be reduced by replacing the lines (word lines or bit lines), for which defective cells are detected at a wafer testing time, by redundant lines.
Japanese Patent Laid-Open No. 4-232688/1992 has disclosed a DRAM which is intended to elongate a refresh cycle. This DRAM includes a plurality of redundant memory cells, a decoder for fetching the addresses of the memory cells and a switch circuit, and the refresh cycle is so adjusted as to become longer for the normal memory cells than that for the defective cells having inferior information holding characteristics. The decoder generates a first output when the fetched address is the one of a normal memory cell, and a second output when the fetched address is the one of a defective cell. The switch circuit is adapted to block an access to the defective cell by allowing the access to the relief cells in response to the first output.
Japanese Patent Laid-Open No. 7-244997/1995 has disclosed a DRAM which can use word lines (word lines connected with a defective cell having inferior information holding characteristics) having a leakage trouble, without increasing the chip size. This DRAM is equipped in its redundancy address decoder with memory means (fuse) for indicating that a trouble of a word line assigned to a redundant one is a leakage trouble, and is given a function to bring the word line and the redundant word line simultaneously into a selected state if the trouble of the word line assigned to the redundant one is the leakage trouble. Consequently even when the redundant word line assigned to the word line having the leakage trouble has a similar leakage trouble, this trouble can be relieved by doubling the substantial information storage capacity of the memory cells.
Japanese Patent Laid-Open No. 1-213900/1989 has disclosed a semiconductor memory device which is equipped with a redundancy circuit having a high-performance sense amplifier connected with relief cells so as to relieve the sense amplifier fault, caused by an erroneous operation due to noise. This sense amplifier is hardly influenced by noise because it is so constructed as to include MOS transistors of high driving ability, which have a larger gate length and width than those of MOS transistors constituting a sense amplifier connected with normal memory cells. As a result, the sense amplifier, connected with the normal memory cells, can be reliably relieved even if it is erroneously operated because of noise.
Japanese Patent Laid-Open No. 4-67669/1992 has disclosed a semiconductor memory device in which the degree of miniaturization (the sizes and spacings of transistors, bit lines and word lines constituting a redundancy circuit) of a redundancy circuit is set larger than that of a main circuit part so as to avoid the fault of the redundancy circuit, as might otherwise be caused by dust or the like.
According to our investigations, the above-specified defect relieving techniques of the prior art have the following problems.
The refresh time period of the DRAM becomes longer as the degree of integration becomes higher in accordance with the JEDEC (Joint Electron Device Engineering Council) standards. As the degree of integration rises, the memory cell size is more miniaturized to shorten the element isolation length, so that the junction field intensity is raised because the substrate density is set high. As a result, the leakage current due to the electric field increases to shorten the information holding time period of the memory cells. With the increase in the degree of integration, the number of defective cells having information holding time periods shorter than the standards increases, so that the number of relief cells has to be enlarged.
When the structure and size of the relief cells are identical to those of the normal memory cells, however, the probability that cells having short information holding time periods are contained even after the relief is enhanced if the number of relief cells is enlarged for every increase in the degree of integration. Assume that relief of several tens of bits is necessary for a DRAM of 64 Mbits (mega bits), relief of several hundreds of bits is necessary for a DRAM of 256 Mbits, and relief of several thousands of bits is necessary for a DRAM of 1 Gbits (giga bits). Four bit lines are replaced for relieving 1 bit, so that about one thousand bits (256 bitsxc3x974) must be replaced. In DRAMs of 64 Mbits, 256 Mbits and 1 Gbits, therefore, several tens Kbits, several hundreds of Kbits and several Mbits must be respectively replaced. As the degree of integration rises, therefore, the probability that faulty bits are contained in the relief cells even after the relief rises. The drops in the production yield due to this fault are 1% or less, several % to about 10%, and several tens % to 100%, respectively, for DRAMs of 64 Mbits, 256 Mbits and 1 Gbits. In other words, arises a problem that the production yield becomes lower for every increase in degree of integration.
The defect relieving structure disclosed in Japanese Patent Laid-Open No. 4-232688/1992 leads to a complicated manufacture process because it has to be additionally equipped with a circuit (nonvolatile memory) for storing the addresses of the normal cells and the defective cells. Moreover, the chip area is enlarged because the structure has to be additionally equipped with a peripheral circuit for making an access to the relief cells in a circuit manner. Likewise, the defect relieving structure disclosed in Japanese Patent Laid-Open No. 7-244997/1995, cannot be free from the increase in the chip area because it also has to be additionally equipped with a peripheral circuit for selecting a word line and a redundant word lines doubly.
The structure (disclosed in Japanese Patent Laid-Open No. 1-213900/1989), in which a high-performance sense amplifier is connected with the relief cells, cannot be a countermeasure against the aforementioned problem that the probability of containing the cells having a short information holding time period even after the relief becomes higher as the number of relief cells is increased more for every increase in degree of integration.
The structure (disclosed in Japanese Patent Laid-Open No. 4-67669/1992), in which the degree of miniaturization of the redundancy circuit is made higher than that of the main circuit part, raises no problem in fabrication and layout when applied to an SRAM (Static Random Access Memory), for example. However, there arises a serious problem in constructing the cells when applied to a DRAM. Moreover, the extension of the information holding time period or the problem intrinsic to DRAMs cannot be realized even if only the sizes and spacings of the transistors, bit lines and word lines constituting the redundancy circuit are made larger than those of the main circuit part.
An object of the invention is to provide a technique capable of extending the refresh time period of the relief cells of a DRAM with inviting neither a drastic increase in the chip area nor a complexity of the process.
The above-specified object and other objects and novel features of the invention will become apparent from the following description with reference to the accompanying drawings.
The summary of representatives of the aspects of the invention to be disclosed herein will be briefly described in the following.
(1) According to the invention, there is provided a semiconductor integrated circuit device comprising a DRAM having a plurality of memory cells and a plurality of relief cells formed in a memory array, wherein the element isolation width of the region having the relief cells is made larger than that of the region having the memory cells.
(2) In a semiconductor integrated circuit device, the impurity concentration of a semiconductor substrate under an element isolation region in the region having the relief cells is lower than that of a semiconductor substrate under an element isolation region in the region having the memory cells.
(3) In a semiconductor integrated circuit device, the spacings of bit lines to be connected with the relief cells are larger than those of bit lines to be connected with the memory cells.
(4) In a semiconductor integrated circuit device, each of the memory cells and the relief cells includes a memory cell selecting MISFET and an information storing capacitive element connected in series with the MISFET, and the lower electrodes of the information storing capacitive element in the relief cells have a larger occupation area than that of the lower electrodes of the information storing capacitive elements in the memory cells.
(5) In a semiconductor integrated circuit device, each of the memory cells and the relief cells includes a memory cell selecting MISFET and an information storing capacitive element connected in series with the MISFET, and under the sources and drains of the memory cell selecting MISFETs in the memory cells and under the sources and drains of the memory cell selecting MISFETs in the relief cells, there are formed field relaxation layers of the same conductivity type as that of the sources and drains.
(6) In a semiconductor integrated circuit device, the element isolation is achieved by a field oxide film which is formed by a local oxidation method.
(7) In a semiconductor integrated circuit device, the element isolation width of the region having the relief cells is 1.5 to 2 times as large as that of the region having the memory cells.
(8) According to the invention, there is provided a semiconductor integrated circuit device comprising a DRAM having a plurality of memory cells and a plurality of relief cells formed in a memory array, wherein the width of the active region having the relief cells is larger than the active region having the memory cells.
(9) In a semiconductor integrated circuit device, each of the memory cells and the relief cells includes a memory cell selecting MISFET and an information storing capacitive element connected in series with the MISFET, and a through hole for connecting one of the source and drain of each memory cell selecting MISFET in the relief cells to the lower electrode of the information storing capacitive element has mutually different diameters in a first direction and in a second direction perpendicular to the first direction.
(10) According to the invention, there is provided a semiconductor integrated circuit device comprising a DRAM having a plurality of memory cells and a plurality of relief cells formed in a memory array, wherein the element isolation width of the region having the relief cells is larger than that of the region having the memory cells, and wherein the width of the active region having the relief cells is larger than the active region having the memory cells.
(11) According to the invention, there is provided a semiconductor integrated circuit device comprising a DRAM having a plurality of memory cells and a plurality of relief cells formed in a memory array, wherein side wall spacers formed on the side walls of the gate electrode of the MISFET included in each of the relief cells are thicker than side wall spacers formed on the side walls of the gate electrode of the MISFET included in each of the memory cells.
(12) According to the invention, there is provided a semiconductor integrated circuit device comprising a DRAM having a plurality of memory cells and a plurality of relief cells formed in a memory array, wherein a gate insulating film of the MISFET included in each of the relief cells is thicker than a gate oxide film of the MISFET included in each of the memory cells.
(13) According to the invention, there is provided a semiconductor integrated circuit device comprising a DRAM having a plurality of memory cells and a plurality of relief cells formed in a memory array, wherein the number of the relief cells to be connected with one redundant bit line is smaller than that of the memory cells to be connected with one bit line.
(14) According to the invention, there is provided a semiconductor integrated circuit device comprising a DRAM having a plurality of memory cells formed in a memory array and including relief cells, wherein a sense amplifier to be used for relief is connected with a first bit line or a signal line of the information of a noted bit and a second bit line or a signal line of the opposit information of the noted bit, and wherein one of two cells to be selected by a predetermined word line is connected with the first bit line whereas the other cell is connected with the second bit line.
(15) According to the invention, there is provided a semiconductor integrated circuit device comprising a DRAM having a plurality of memory cells formed in a memory array and including relief cells, wherein a sense amplifier to be used for relief is connected with a first bit line or a signal line of the information of a noted bit and a second bit line or a signal line of the opposit information of the noted bit, and wherein one of two word lines to be simultaneously selected selects the cell connected with the first bit line whereas the other selects the cell connected with the second bit line.
(16) According to the invention, there is provided a semiconductor integrated circuit device comprising a DRAM having a plurality of memory cells formed in a memory array and including relief cells, wherein a sense amplifier to be used for relief is connected with two first bit lines or signal lines of the information of a noted bit and two second bit lines or signal lines of the opposit information of the noted bit, and wherein one of two word lines to be simultaneously selected selects the cell connected with one of the two first bit lines whereas the other selects the cell connected with one of the two second bit lines.
(17) According to the invention, there is provided a process for manufacturing a DRAM having a plurality of normal cells and a plurality of relief cells formed in a memory array, comprising:
(a) thermally treating a semiconductor substrate to form a first gate insulating film on the surface thereof and then selectively removing the first gate insulating film of the normal cell region;
(b) thermally treating the semiconductor substrate again to form a second gate insulating film in the normal cell region, and making the first gate insulating film in the relief cell region thicker than the second gate insulating film;
(c) forming gate electrodes of the normal cells over the second gate insulating film of the normal cell region and gate electrodes of the relief cells over the first gate insulating film of the relief cell region by patterning the first conductive film deposited on the semiconductor substrate;
(d) forming sources and drains of the normal cells over the semiconductor substrate in the normal cell region and sources and drains of the relief cells over the semiconductor substrate in the relief cell region;
(e) forming first side wall spacers on the side walls of the gate electrodes in the normal cell region by depositing a first insulating film on the semiconductor substrate, and by etching the first insulating film in the normal cell region selectively;
(f) forming second side wall spacers thicker than the first the wall spacers on the side walls of the gate electrodes in the relief cell region by depositing a second insulating film on the semiconductor substrate, and by etching the second insulating film;
(g) forming contact holes individually over either the sources or drains of said normal cells and over either the sources or drains of the relief cells by etching a third insulating film deposited on the semiconductor substrate; and
(h) forming capacitive elements for storing the information stored in the normal cells and capacitive elements for storing the information stored in the relief cells individually over the third insulating film.
(18) In a semiconductor integrated circuit device manufacturing process, after the contact holes are individually formed over either the sources or drains of the normal cells and over either the sources or drains of the relief cells by etching a third insulating film deposited on the semiconductor substrate, a polycrystalline silicon film containing an impurities of the same conductivity type as that of the sources and drains is buried in the contact holes.